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IDT74ALVC16260 3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS
* 0.5 MICRON CMOS Technology * Typical tSK(o) (Output Skew) < 250ps * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * VCC = 3.3V 0.3V, Normal Range * VCC = 2.7V to 3.6V, Extended Range * VCC = 2.5V 0.2V * CMOS power levels (0.4 W typ. static) * Rail-to-Rail output swing for increased noise margin * Available in SSOP, TSSOP, and TVSOP packages
IDT74ALVC16260
FEATURES:
DESCRIPTION:
DRIVE FEATURES:
* High Output Drivers: 24mA * Suitable for heavy loads
APPLICATIONS:
* 3.3V high speed systems * 3.3V and lower voltage computing systems
This 12-bit to 24-bit multiplexed D-type latch is built using advanced dual metal CMOS technology. The ALVC16260 is used in applications in which two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or demultiplexing address and data information in microprocessor or bus-interface applications. This device also is useful in memory interleaving applications. Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available for address and/or data transfer. The output-enable (OE2B, OE2B, and OEA) inputs control the bus transceiver functions. The OE2B and OE2B control signals also allow bank control in the A-to-B direction. Address and/ or data information can be stored using the internal storage latches. The latch-enable (LE1B, LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is high, the latch is transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains latched until the latch-enable input is returned high. The ALVC16260 has been designed with a 24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.
FUNCTIONAL BLOCK DIAGRAM
OE1B LEA1B
29 30
A-1B LATCH
12
1B1:12
LE1B SEL OEA
2
12
28 1
1B-A LATCH
12
12
A1:12
12
M U X
1
0
12 12
LE2B
27
2B-A LATCH
12
LEA2B OE2B
55
A-2B LATCH
2B 1:12
12
56
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
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(c) 1999 Integrated Device Technology, Inc.
MARCH 1999
DSC-4536/2
IDT74ALVC16260 3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
O EA LE1B
2B 3
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 OE2B LEA2B
2B4
Unit V V C mA mA mA mA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
VTERM(2) VTERM(3) TSTG IOUT IIK IOK
Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VI > VCC Continuous Clamp Current, VO < 0 Continuous Current through each VCC or GND
-0.5 to +4.6 -0.5 to VCC+0.5 -65 to +150 -50 to +50 50 -50 100
GND
2B 2 2B 1
GND
2B5 2B6
VCC A1 A2 A3 GND A4 A5 A6 A7 A8 A9 GND A10 A11 A12 VCC
1B 1 1B 2
VCC
2B 7 2B 8 2B9
ICC ISS
GND
2B10 2B 11 2B12 1B 12 1B 11 1B 10
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC.
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT COUT Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 5 7 7 Max. 7 9 9 Unit pF pF pF
GND
1B 9 1B 8 1B 7
NOTE: 1. As applicable to the device type.
VCC
1B 6 1B 5
GND
1B3
GND
1B 4
FUNCTION TABLES(1)
B-TO-A (OEB = H)
Inputs 1Bx H 2Bx X SEL H LE1B H LE2B X OEA L Output Ax H
LE2B SEL
LEA1B OE1B
SSOP/ TSSOP/ TVSOP TOP VIEW
L
X X X X X
X
X H L X X
H
H L L L X
H
L X X X X
X
X H H L X
L
L L L L H
L
A0
(2)
H L A0
(2)
Z
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IDT74ALVC16260 3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
INDUSTRIAL TEMPERATURE RANGE
FUNCTION TABLES (CONTINUED)(1)
A-TO-B (OEA = H)
Inputs Ax H L H L H L X X X X X LEA1B H H H H L L L X X X X LEA2B H H L L H H L X X X X OE1B L L L L L L L H L H L OE2B L L L L L L L H H L L H L H L 1B0
(2)
Outputs 1Bx 2Bx H L 2B0 2B0
(2) (2)
H L
2B0 Z Z Active Active
(2)
(2) 1B0 (2) 1B0
Z Active Z Active
NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance = LOW-to-HIGH transition 2. Output level before the indicated steady-state input conditions were established.
PIN DESCRIPTION
Pin Names Ax (1:12) 1Bx (1:12) 2Bx (1:12) LEA1B LEA2B LE1B LE2B SEL OEA OE1B OE2B I/O I/O I/O I/O I I I I I I I I Description Bidirectional Data Port A. Usually connected to the CPU's address/data bus. Bidirectional Data Port 1B. Usually connected to the even path or even bank of memory. Bidirectional Data Port 2B. Usually connected to the odd path or odd bank of memory. Latch Enable Input for A-1B Latch. The latch is open when LEA1B is HIGH. Data from the A-port is latched on the HIGH to LOW transition of LEA1B Latch Enable Input for A-2B Latch. The latch is open when LEA2B is HIGH. Data from the A-port is latched on the HIGH to LOW transition of LEA2B Latch Enable Input for 1B-A Latch. The latch is open when LE1B is HIGH. Data from the A-port is latched on the HIGH to LOW transition of LE1B Latch Enable Input for 2B-A Latch. The latch is open when LE2B is HIGH. Data from the A-port is latched on the HIGH to LOW transition of LE2B 1B or 2B Port Selection. When HIGH, SEL enables data transfer from 1B Port to A Port. When LOW, SEL enables data transfer from 2B Port to A Port. Output Enable for A Port (Active LOW) Output Enable for 1B Port (Active LOW) Output Enable for 2B Port (Active LOW)
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IDT74ALVC16260 3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = -40C to +85C
Symbol VIH VIL IIH IIL IOZH IOZL VIK VH ICCL ICCH ICCZ ICC Parameter Input HIGH Voltage Level Input LOW Voltage Level Input HIGH Current Input LOW Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 2.3V, IIN = -18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC One input at VCC - 0.6V, other inputs at VCC or GND VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.6V VI = VCC VI = GND VO = VCC VO = GND Test Conditions Min. 1.7 2 -- -- -- -- -- -- -- -- -- Typ.(1) -- -- -- -- -- -- -- -- -0.7 100 0.1 Max. -- -- 0.7 0.8 5 5 10 10 -1.2 -- 40 V mV A A A A V Unit V
Quiescent Power Supply Current Variation
--
--
750
A
NOTE: 1. Typical values are at VCC = 3.3V, +25C ambient.
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V IOH = - 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA Test Conditions(1) VCC = 2.3V to 3.6V IOH = - 0.1mA IOH = - 6mA IOH = - 12mA Min. VCC - 0.2 2 1.7 2.2 2.4 2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55 V Unit V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to + 85C.
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IDT74ALVC16260 3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
INDUSTRIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, TA = 25C
VCC = 2.5V 0.2V Symbol CPD CPD Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical 37 4 VCC = 3.3V 0.3V Typical 41 7 Unit pF
SWITCHING CHARACTERISTICS(1)
VCC = 2.5V 0.2V Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tW tSK(O) Parameter Propagation Delay Ax to 1Bx or Ax to 2Bx Propagation Delay 1Bx to Ax or 2Bx to Ax Propagation Delay LEXB to Ax Propagation Delay LE1B to 1BX or LEA2B to 2Bx Propagation Delay SEL to Ax Output Enable Time OEA to Ax, OE1B to 1Bx, or OE2B to 2Bx Output Disable Time OEA to Ax, OE1B to 1Bx, or OE2B to 2Bx Set-up Time, data before LE1B, LE2B, LEA1B, LEA2B Hold Time, data after LE1B, LE2B, LEA1B, LEA2B Pulse Duration, LE1B, LE2B, LEA1B, or LEA2B HIGH Output Skew(2) 1.4 1.1 3.3 -- -- -- -- -- 1.1 1.9 3.3 -- -- -- -- -- 1.1 1.5 3.3 -- -- -- -- 500 ns ns ns ps 1 5.7 -- 5 1.3 4.6 ns 1 6.7 -- 6.4 1 5.4 ns 1 6.9 -- 6.6 1.1 5.6 ns 1 5.6 -- 5.2 1 4.4 ns 1 5.6 -- 5.2 1 4.4 ns 1 5.4 -- 5.1 1.2 4.3 ns Min. 1 Max. 5.4 -- VCC = 2.7V Min. Max. 5.1 VCC = 3.3V 0.3V Min. 1.2 Max. 4.3 Unit ns
NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = - 40C to + 85C. 2. Skew between any two outputs of the same package and switching in the same direction.
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IDT74ALVC16260 3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
INDUSTRIAL TEMPERATURE RANGE
VIH VT 0V VOH VT VOL VIH VT 0V
ALV C Link
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V0.3V VCC(1)= 2.7V 6 2.7 1.5 300 300 50
VCC 500 Pulse Generator
(1, 2)
SAME PHASE INPU T TRAN SITION
VCC(2)= 2.5V0.2V 2 x Vcc Vcc Vcc / 2 150 150 30
Unit V V V mV mV pF
VLOAD Open GND
tPLH OU TPUT tPLH OPPOSITE PHASE INPU T TRAN SITION
tPHL
6 2.7 1.5 300 300 50
tPHL
Propagation Delay
ENABLE CON TROL IN PUT tPZL
DISABLE
VIN D .U .T.
VOUT
VIH VT 0V VLOAD/2 VOL + VLZ VOL VOH VOH - VHZ 0V
ALV C Link
tPLZ VLOAD/2 VT tPHZ VT 0V
RT
500 CL
ALVC Link
Test Circuit for All Outputs
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2ns; tR 2ns.
OUTPU T SW ITCH NOR MALLY CLO SED LOW tPZH OU TPUT SW ITCH NORMALLY O PE N H IGH
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V
ALVC Link
Enable and Disable Times
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open
VIH INPU T VT 0V VOH OUTPUT 1 VT VOL VOH OUTPUT 2 tPLH2 tPHL2
ALVC Link
DATA INPUT TIMING INPU T ASYNC HRON OU S CON TROL SYNC HRON OU S CON TROL
tSU
tH
tREM
tSU
tH
Set-up, Hold, and Release Times
tPLH1
tPHL1
LOW -H IGH -LOW PULSE tW HIGH-LOW -HIGH PULSE
VT
tSK (x)
tSK (x)
VT
ALVC Link
VT VOL
Pulse Width
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
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IDT74ALVC16260 3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT ALVC X XX Bus-Hold Temp. Range XX Family XX XXX Device Type Package
PV PA PF 260 16
Shrink Small Outline Package Thin Shrink Small Outline Package Thin Very Small Outline Package 12-Bit to 24-Bit Multiplexed D-Type Latch with 3-State Outputs Double-Density, 24mA
Blank No Bus-Hold 74 -40C to +85C
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